Electrostatic Applications
Basic ESD and I/O Design
Sanjay Dabral, Timothy J. Maloney
(1998) 328 pages
Book Description: The first comprehensive guide to ESD protection and I/O design Basic ESD and I/O Design is the first book devoted to ESD (electrostatic discharge) protection and input/output design. Addressing the growing demand in industry for high-speed I/O designs, it bridges the gap between ESD research and current VLSI design practices and provides a much-needed reference for practicing engineers who are frequently called upon to learn the subject on the job.
This volume presents an integrated treatment of This volume presents an integrated treatment of ESD, I/O, and process parameter interactions that both I/O designers and process designers can use. It examines key factors in I/O and ESD design and testing, and helps the reader consider ESD and reliability issues up front when making I/O choices. Emphasizing clarity and simplicity, this book focuses on design principles that can be applied widely as this dynamic field continues to evolve. Basic ESD and I/O Design:
Describes strategies for design-oriented ESD protection; Explains layout methods that enhance ESD protection designs; Addresses basic I/O designs, including new problems such as mixed; voltage interfaces; Discusses fabrication aspects affecting ESD and I/O protection; Illustrates concepts using numerous figures and examples; Expresses device physics in terms of simple electrical circuit models; Cross-references the material to standard texts in the field
Essential for engineers in industry and anyone designing circuits, systems, or devices for future technologies, Basic ESD and I/O Design is also a useful reference for researchers and graduate students involved in core VLSI design or computer architecture.
From the Back Cover : "The first comprehensive guide to ESD protection and I/O design Basic ESD and I/O Design is the first book devoted to ESD (electrostatic discharge) protection and input/output design. Addressing the growing demand in industry for high-speed I/O designs, it bridges the gap between ESD research and current VLSI design practices and provides a much-needed reference for practicing engineers who are frequently called upon to learn the subject on the job.
Contents
INTRODUCTION
Historical Perspective; Nature of ESD and Approximating Models; ESD Relevant to Semiconductor Chips; ESD-Related Failures; ESD Issues in the Future; I/O Pin Trends and Sensitivity of Increased Technology; Increased Number of Technologies; Other Complications; Solutions; Outline of the Book; Summary; References
ESD PROTECTION METHODOLOGY
Additional Issues Due to ESD; Devices for ESD Protection; Thick-Field-Oxide (TFO) Clamps; Grounded-Gate NMOS (GGNMOS); Silicon-Controlled Rectifier (SCR); Medium-Voltage Triggered SCR (MVTSCR); Low-Voltage Triggered SCR (LVTSCR); Bimodal SCR; Gate-Coupled NMOS (GGNMOS); Punchthrough-Induced Protection Element (PIPE); Spark Gap; Zener Clamps; Double-Implant Field Inversion Device in Well; (DIFIDW); Electrothermal Simulation; Non-Breakdown Devices; Diodes; Cascaded Diodes; MOSFETs; Current Path Construction; I/O Pad Segment; Dual-Diode Based; BiCMOS BJT Based; MOS Based; Power Supply Coupling Segment; Diode Based; MOS Based; Vcc-to-Vss Core Clamps; MOS Based; Diode Clamps; Cantilevered Diode; CDM Guidelines; Summary; References
ADDITIONAL ESD CONSIDERATIONS
Capacitor Benefits in Stress Reduction; Packaging Effects on ESD; Conventional Packaging; Multichip Modules; Small-Chip ESD Issues; Benefits of Distributed Clamps; Predriver Designs; Antenna Diode Issues; Hot-Electron Interactions; Latchup Issues; Silicon-on-Insulator ESD Protection; Summary; References
CIRCUITS
Transmission Line Phenomena; Series and Parallel Termination; CMOS I/O; Gunning Transceiver Logic (GTL) I/O; Bus Timing Considerations; Common Clock Transfers; Cotransmitted Clock (CTC); Pulse Width Modulation Scheme; Topology Effects; Bidirectional Signaling; Compensation Schemes; Analog Compensation; Digital Compensation; Frequency-Based Compensation; Simultaneous Switching Output Noise; Design for SSO Reduction; Predriver Skewing; NP-Inverted Stack Driver; Differential Signaling; SSO Reduction Using Packaging Options; SSO Reduction Using Low- Weight Coding; System Modeling; I/O Information on the Internet; Summary; References
LAYOUT ISSUES
Output Transistor Layout; Thick-Field Oxide (TFO) Layout; Diode Layout; Decoupling Capacitors; SCR Layout; Antenna Diode Layout; Resistor Layouts; Periphery Layout; Power Delivery; I/O Routing Channels; Metal Design Rules; ESD Layout Verification; Manual ESD Verification; Automated Verification; Summary; References
ESD AND 1/0 INTERACTIONS
I/O Performance Trade-off; Impact on Output Buffer Sizing Granularity; Impact on Compensation Scheme Implementation; Input Pass Transistor Jitters; Other Interactions; Periphery Noise Coupling into Core Supplies; I/O and Core Switching Current Characteristics; Peripheral Noise Coupling Through ESD Diodes; Peripheral Noise and Power System Impedance Interaction; ESD Diodes and I/O Signal Integrity; High-Frequency Leakage in I/O; Summary; References
MIXED-VOLTAGE ESD
Mixed-Voltage Input Design; Input Design for Low-Voltage Core and High-Voltage I/O; Input Design for High-Voltage Core and Low-Voltage I/O; Capacitive-Coupled Input Receiver; Output Design for Mixed Voltage; Open-Drain Design for High-Voltage I/O; CMOS Buffer Design for High-Voltage I/O; Output Predrivers for High-Voltage I/O; Effect on Power Supply Coupling Diodes; Separate ESD Bus; Back Biasing; Process Modifications to Support High Voltages; Summary; References
ESD RELIABILITY MEASUREMENT AND FAILURE ANALYSIS BASICS
Simple ESD Instrumentation; HBM Instrumentation; CDM Instrumentation; Transmission Line Stress Box; Burn-in Testing; Failure Analysis; Electrical Evaluation; Correlation Between EOS and ESD; HBM and MM Correlation; Microscopy; Summary; References
CONCLUSION
Summary
Future Questions
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