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Modeling of Electrical Overstress in Integrated Circuits

Carlos H. Diaz, Sung-Mo Kang, Charvaka Duvvury


xvix + 148 pages

This book covers techniques for modeling electrical overstress and electrostatic discharge failures in integrated circuits. It is written at a technical level for engineers, designers, and specialists in the fields of EOS/ESD and power failures. A good reference to have in your library.


Electrical overstress in ICS:

Definition of electrostatic discharge phenomena
Impact of ESD on IC chip technologies
Protection strategies for reducing esd effects
ESD models and qualification
EOS models and qualification
Previous work on ESD/EOS device failure modeling

NMOS ESD protection devices and process related issues:

ESD phenomena in NMOS devices
Failure modes in NMOS
Protection technique using NMOS device structures
The impact of process technologies on NMOS ESD behavior
Advance NMOS device protection concepts
Measuring EOS robustness in ICS:
Statistical distribution ofEOS/ESD-related failures
Characterization of bipolar devices
EOS characterization of NMOS devices

EOS thermal failure simulation for integrated circuits:

ITSIM: a nonlinear thermal failure simulator for ICS
Simulation results for ceramic and plastic packages

ITSIM: a nonlinear 2D-1D thermal simulator:

Running the program
Input file
An example
2D electrothermal analysis of Device failure in MOS processes:
Device level electrothermal simulation
Comparison of experimental and 2D electrothermal results

Circuit level electrothermal simulation:

Temperature effects and device models
Simulation of avalanche breakdown
Temperature model for electrothermal simulation
IETSIM: an electrothermal circuit-level simulation tool

IETSIM: an electrothermal circuit simulator:

Running the program
Input file: circuit description and format

Summary and future research.